DIG ADC common configuration
| START_FORCE | 0: select FSM to start SAR ADC. 1: select software to start SAR ADC. |
| START | Start SAR ADC by software. |
| WORK_MODE | 0: single-channel scan mode. 1: double-channel scan mode. 2: alternate-channel scan mode. |
| SAR_SEL | 0: select SAR ADC1. 1: select SAR ADC2, only work for single-channel scan mode. |
| SAR_CLK_GATED | SAR clock gate enable bit. |
| SAR_CLK_DIV | SAR clock divider |
| SAR1_PATT_LEN | 0 ~ 15 means length 1 ~ 16 |
| SAR2_PATT_LEN | 0 ~ 15 means length 1 ~ 16 |
| SAR1_PATT_P_CLEAR | Clear the pointer of pattern table for DIG ADC1 CTRL. |
| SAR2_PATT_P_CLEAR | Clear the pointer of pattern table for DIG ADC2 CTRL. |
| DATA_SAR_SEL | 1: sar_sel will be coded to the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. |
| DATA_TO_I2S | 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix |
| XPD_SAR_FORCE | Force option to xpd sar blocks. |
| WAIT_ARB_CYCLE | Wait arbit signal stable after sar_done. |